Digital Circuits Commons^™

0.18Μm Cmos Low Power Adpll With A Novel Local Passive Interpolation Time-To-Digital Converter Based On Tri-State Inverter, Moon Seok Kim

Electrical and Computer Engineering Master's Theses

The objective of the thesis is to design a novel ADPLL with local passive interpolation time-to-digital (LPI-TDC) based on a tri-state inverter for clock synchronization, clock recovery, and noise and jitter suppression in modern microprocessors. When compared to traditional implementations of PLLs, an all-digital approach turns out to be more suitable for the integrated circuits in order to improve overall system timing issues.

In order to accomplish a fast lock of ADPLL, the higher resolution of TDC is needed. An All-Digital Phase-Locked Loop (ADPLL) design is proposed to achieve short locking time using a circuitry of the LPI-TDC based on ...

Self-Calibrated Wireless Sleep Sensing System For Brain Injury Diagnostics, Ali Abedi, Frederick Schwaner, E Mougharbel, M J. Hayes

WiSe-Net Laboratory

A wide range of conditions fall under the category of Mild Traumatic Brain Injury (mTBI) diagnosis. In this article, we focus on a new method during sleep to detect mTBI associated with neuro-cognitive impairment that is not apparent using standard neuro-imaging methods. A wireless pressure sensor system comprising a piezo-resistive flexible substrate paired with a microcontroller and a radio is designed and built to provide information relevant to mTBI detection. The collected information is then processed with a software program to remove noise and interference, and detect both sleep states and cardio-respiratory movements.

Wireless Sensors Without Batteries, Ali Abedi

WiSe-Net Laboratory

No abstract provided.

Air: Adaptive Dynamic Precision Iterative Refinement, Jun Kyu Lee

Doctoral Dissertations

In high performance computing, applications often require very accurate solutions while minimizing runtimes and power consumption. Improving the ratio of the number of logic gates implementing floating point arithmetic operations to the total number of logic gates enables greater efficiency, potentially with higher performance and lower power consumption. Software executing on the fixed hardware in Von-Neuman architectures faces limitations on improving this ratio, since processors require extensive supporting logic to fetch and decode instructions while employing arithmetic units with statically defined precision. This dissertation explores novel approaches to improve computing architectures for linear system applications not only by designing application-specific ...

A Formal Approach To Concurrent Error Detection In Fpga Luts, Jameson P. Bergstra

Open Access Dissertations and Theses

In this thesis we discuss a formal approach to the design of concurrent error detection (CED) logic in field-programmable gate arrays (FPGAs). Single event upsets (SEUs) occurring in look-up table (LUT) configuration bits are considered as the fault model. Our approach involves representing the LUT network of the design implemented in the FPGA with constraints to model the presence of SEUs as a boolean formula in conjunctive normal form. A quantified boolean formula (QBF) based approach to designing CED logic based on parity check codes is found to be infeasible for designs of a realistic size. It is shown that ...

A Pipelined, Single Precision Floating-Point Logarithm Computation Unit In Hardware, Jing Chen

Open Access Dissertations and Theses

A large number of scientific applications rely on the computing of logarithm. Thus, accelerating the speed of computing logarithms is significant and necessary. To this end, we present the realization of a pipelined Logarithm Computation Unit (LCU) in hardware that uses lookup table and interpolation techniques. The presented LCU supports single precision arithmetic with fixed accuracy and speed. We estimate that it can generate 2.9G single precision values per second under a 65nm fabrication process. In addition, the accuracy is at least 21 bits while lookup table size is about 7.776KB. To the best of our knowledge, our ...

Riley The Cat, Nicholas Zankich

Computer Engineering

There are many toys that exist that are comfort objects. Generally these are toys that are soft such as blankets, stuffed animals, and pillows. Robotic toys also exist such as games, interactive books, and instruments. There exists a crossover market that includes Furbys, Tomagachi pets, and Fur Real Friends. While being very popular, I believe that this crossover isn’t perfect, and that there is a lot of room for improvement. Riley (Figure 1) was created to make something that is both completely a robot and a comfort object.

Design And Simulation Of Interconnected H-Bridge Inverter, Samuel Muehleck

Computer Engineering

In this project, the research, design and simulation of an interconnected H-bridge single-phase inverter was explored. The inverter design was divided into three separate sections. First, a VHDL programmed CPLD was used to generate control signals for the transistors of the inverter circuit. Second, power electronics was used to create an inverter circuit to change a DC input to a 60 Hz AC output. Lastly, additional circuits were used to link the generated control signals to the MOSFET transistors of the inverter circuit. The operation of the three components was then validated with computer simulations. Results of computer simulation demonstrate ...