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Lmproving Microcontroller And Computer Architecture Education Through Software Simulation, Kevin Brightwell 2017 The University of Western Ontario

Lmproving Microcontroller And Computer Architecture Education Through Software Simulation, Kevin Brightwell

Electronic Thesis and Dissertation Repository

In this thesis, we aim to improve the outcomes of students learning Computer Architecture and Embedded Systems topics within Software and Computer Engineering programs. We develop a simulation of processors that attempts to improve the visibility of hardware within the simulation environment and replace existing solutions in use within the classroom. We designate a series of requirements of a successful simulation suite based on current state-of-the-art simulations within literature. Provided these requirements, we build a quantitative rating of the same set of simulations. Additionally, we rate our previously implemented tool, hc12sim, with current solutions. Using the gaps in implementations from ...


Energy And Performance Balancing Architecture For Asynchronous Data Processing Platforms, Chien-Wei Lo 2017 University of Arkansas, Fayetteville

Energy And Performance Balancing Architecture For Asynchronous Data Processing Platforms, Chien-Wei Lo

Theses and Dissertations

The semiconductor industry has been increasingly focused on the energy consumption and heat generation in CMOS-based integrated circuits (ICs) for its dominating impact on the system performance and reliability. Without clock-related timing constraints, asynchronous circuits have demonstrated unique flexibility in performance-energy tradeoffs compared to synchronous designs. This dissertation work presents the architecture capable of balancing energy and performance for asynchronous digital signal processing circuits using the Multi-Threshold NULL Convention Logic (MTNCL). Architecture implementing user-configurable adaptive dynamic voltage scaling (DVS) and data processing core disabling based on the detection and parameterization of system throughput are developed for MTNCL parallel homogeneous and ...


One-To-Cloud One-Time Pad Data Encryption: Introducing Virtual Prototyping With Pspice, Paul Tobin, Lee Tobin, Roberto Gandia Blanquer DR, Michael McKeever, Jonathan Blackledge Professor 2017 Dublin Institute of Technology

One-To-Cloud One-Time Pad Data Encryption: Introducing Virtual Prototyping With Pspice, Paul Tobin, Lee Tobin, Roberto Gandia Blanquer Dr, Michael Mckeever, Jonathan Blackledge Professor

Conference papers

In this paper, we examine the design and application of a one-time pad encryption system for protecting data stored in the Cloud. Personalising security using a one-time pad generator at the client-end protects data from break-ins, side-channel attacks and backdoors in public encryption algorithms. The one-time pad binary sequences were obtained from modified analogue chaos oscillators initiated by noise and encoded client data locally. Specific ``one-to-Cloud'' storage applications returned control back to the end user but without the key distribution problem normally associated with one-time pad encryption. Development of the prototype was aided by ``Virtual Prototyping'' in the latest version ...


General-Purpose Digital Filter Platform, Michael Cheng 2017 California Polytechnic State University, San Luis Obispo

General-Purpose Digital Filter Platform, Michael Cheng

Electrical Engineering

This senior project provides a platform for high-speed, general-purpose digital filter implementation. EE 459 currently implements digital filters using reprogrammable digital signal processor boards. These aging digital signal processors serially calculate each difference equation term. Operating at 1 Mega-sample per second, the new general-purpose platform simultaneously processes at least ten digital filtering difference equation coefficients. The platform also features an audio jack input and BNC connectors for viewing input and output signals. The filter digitizes single channel audio signals at 44.1 kHz sampling rate with 16-bit precision or 1 MHz sampling at 8-bit precision. The new reprogrammable platform includes ...


Solid State Drive, Shaun A. Steele 2017 California Polytechnic State University, San Luis Obispo

Solid State Drive, Shaun A. Steele

Electrical Engineering

This project documents the design and implementation of a solid state drive (SSD). SSDs are a non-volatile memory storage device that competes with hard disk drives. SSDs rely on flash memory, a type of non-volatile memory that is electrically erased and programmed. The appeal of SSDs lies in the fact that they allow a fast, reliable, and durable memory storage device. The goal of this project is to have a working external SSD built from scratch.


The Following Robot, Juan D. Cerda, Matthew S. Kwan, Vi M. Le 2017 California Polytechnic State University, San Luis Obispo

The Following Robot, Juan D. Cerda, Matthew S. Kwan, Vi M. Le

Computer Engineering

The objective of this project is to design, build, and test an autonomous robot with an associated Android application. The robot uses on board inertial measurement sensors (magnetometer, accelerometer, gyroscope) and coordinates itself through Bluetooth communication with the similar built­in measurement sensors on the Android phone to mimic and follow movement. The Following Robot incorporates the same basic movement functionality as a typical RC car. The robot follows the user’s phone through an application on one’s phone. This application accesses the phone’s accelerometer and gyroscope data and translates into appropriate conversions. Methods of tracking and calculating ...


Poly Drop, Zachary T. Scott, Lilly J. Paul 2017 California Polytechnic State University, San Luis Obispo

Poly Drop, Zachary T. Scott, Lilly J. Paul

Computer Engineering

Poly Drop is a software interface to control an Open Drop digital micro-fluidics system. We obtained a hardware system from Gaudi labs. Our task was to create a Graphical User Interface that made the control of the device easier and more automated for better testing. We created software that had 3 parts: a control GUI, arduino code to control the hardware, and Image Analysis that gives the user information such as location and color of liquid drops as they move across the electrode grid of the Open Drop system. The GUI was developed using Java Swing. The communication between the ...


Power Efficient High Temperature Asynchronous Microcontroller Design, Nathan William Kuhns 2017 University of Arkansas, Fayetteville

Power Efficient High Temperature Asynchronous Microcontroller Design, Nathan William Kuhns

Theses and Dissertations

There is an increasing demand for dependable and efficient digital circuitry capable of operating in high temperature environments. Extreme temperatures have adverse effects on traditional silicon synchronous systems because of the changes in delay and setup and hold times caused by the variances in each device’s threshold voltage. This dissertation focuses on the design of the major functionality of an asynchronous 8051 microcontroller in Raytheon’s high temperature Silicon Carbide process, rated for operation over 300ºC. The microcontroller is designed in NULL Convention Logic, for which the traditional bus architecture used for data transfer would consume a large amount ...


On The Development Of A One-Time Pad Generator For Personalising Cloud Security, Paul Tobin, Lee Tobin, Michael McKeever, Jonathan Blackledge Profesor 2017 Dublin Institute of Technology

On The Development Of A One-Time Pad Generator For Personalising Cloud Security, Paul Tobin, Lee Tobin, Michael Mckeever, Jonathan Blackledge Profesor

Conference papers

Cloud computing security issues are being reported in newspapers, television, and on the Internet, on a daily basis. Furthermore, in 2013, Edward Snowden alleged backdoors were placed in a number of encryption systems by the National Security Agency causing confidence in public encryption to drop even further. Our solution allows the end-user to add a layer of unbreakable security by encrypting the data locally with a random number generator prior to uploading data to the Cloud. The prototype one-time pad generator is impervious to cryptanalysis because it generates unbreakable random binary sequences from chaos sources initiated from a natural noise ...


Recent Semantic Changes For The Term "Digital", Tore Brattli 2016 University of Tromsø

Recent Semantic Changes For The Term "Digital", Tore Brattli

Proceedings from the Document Academy

The term digital originates from the Latin word for finger/counting and has for many years been used to denote discrete signals and information, as opposed to analog. Discrete representation is an important principle, not only in computers, but also for (printed) text, music scores and even our genes. Recently however, the use of the term has increased and the meaning expanded to include almost everything related to information technology, e.g. digital natives and digital addiction. This study investigates the core principles of digital representation and compares this concept with the recent usage, with a focus on Norwegian media ...


Low Power & High Speed Carry Select Adder Design Using Verilog, Somashekhar Malipatil, R. Basavaraju, Praveen kumar Nartam 2016 Bharat Institute of Engineering & Technology, Ibrahimpatnam, Hyderabad

Low Power & High Speed Carry Select Adder Design Using Verilog, Somashekhar Malipatil, R. Basavaraju, Praveen Kumar Nartam

Kirat Pal Singh

The binary addition is the basic arithmetic operation in digital circuits and it became essential in most of the digital systems including ALU, microprocessors and DSP. Adders are the basic building blocks in digital integrated circuit based designs. Ripple Carry Adder (RCA) gives the most compact design but takes longer computation time. The time critical applications use Carry Look-ahead scheme (CLA) to derive fast results but they lead to increase in area. Carry Select Adder is a compromise between RCA and CLA in term of area and delay. This paper focuses on the design analysis of carry select adder based ...


Implementation Of 32-Bit Carry Select Adder Using Brent-Kung Adder, P. Nithin, N. Udaya Kumar, K. Bala Sindhuri 2016 SRKR Engineering College, Bhimavaram

Implementation Of 32-Bit Carry Select Adder Using Brent-Kung Adder, P. Nithin, N. Udaya Kumar, K. Bala Sindhuri

Kirat Pal Singh

The circuit used to add the two numbers or two bits is adder. The main problem with the adder is both the area and delay to produce the final output. So, this paper implements an adder it requires a less amount of delay and area to produce the final output. The reduction of delay and area is done by the Parallel Prefix Adders. It plays a prominent role in Digital Combinational Circuits. Area and power are other factors which really makes the adder effective. The techniques used to get a less amount of delay and area is by using the ...


A System For Monitoring And Managing Indoor Air Quality And Environmental Conditions, Ali Ibrahim 2016 Boise State University

A System For Monitoring And Managing Indoor Air Quality And Environmental Conditions, Ali Ibrahim

Boise State University Theses and Dissertations

The quality of indoor air depends on different types of pollutant sources existing in a semi-enclosed environment. The sources can be biological, chemical, or toxic pollutants. These sources can cause health issues and discomfort for occupants. One of the indicators of poor indoor air quality is Carbon Dioxide (CO2). CO2 can be used to indicate the indoor air exchange rate. The lack of air exchange means higher levels of CO2. High levels of indoor particulates can also be an indication of poor air quality. Due to the lack of fresh air, air circulation, and air filtration, the ...


Asynchronous Data Processing Platforms For Energy Efficiency, Performance, And Scalability, Liang Men 2016 University of Arkansas, Fayetteville

Asynchronous Data Processing Platforms For Energy Efficiency, Performance, And Scalability, Liang Men

Theses and Dissertations

The global technology revolution is changing the integrated circuit industry from the one driven by performance to the one driven by energy, scalability and more-balanced design goals. Without clock-related issues, asynchronous circuits enable further design tradeoffs and in operation adaptive adjustments for energy efficiency. This dissertation work presents the design methodology of the asynchronous circuit using NULL Convention Logic (NCL) and multi-threshold CMOS techniques for energy efficiency and throughput optimization in digital signal processing circuits. Parallel homogeneous and heterogeneous platforms implementing adaptive dynamic voltage scaling (DVS) based on the observation of system fullness and workload prediction are developed for balanced ...


Design Of A High Speed 32-Bit Parallel Hybrid Adder For Digital Arithmetic System, Vaibhav V. Deshmukh, Nitiket N. Mhala 2016 Selected Works

Design Of A High Speed 32-Bit Parallel Hybrid Adder For Digital Arithmetic System, Vaibhav V. Deshmukh, Nitiket N. Mhala

Kirat Pal Singh

Addition is a heavily used basic fundamental arithmetic operation that figures prominently in any digital logic system, digital signal processor, control system and scientific applications. Addition is a very hardware intensive subject and one as users are mostly concerned with getting low smaller area and higher speed. In ALU, adders play a major role not only in addition but it also performing many other basic arithmetic operations like subtraction, multiplication, etc. Hence, realization of an efficient adder is required for better performance of an ALU and therefore the processor. This paper presents the design of 32-bit Parallel Hybrid Adder architectures ...


Comparison Of 32-Bit Hybrid Adders In Vhdl, Viraj V. Gotmare, Pankaj Agrawal 2016 GHRAET, Nagpur, Maharashtra, India

Comparison Of 32-Bit Hybrid Adders In Vhdl, Viraj V. Gotmare, Pankaj Agrawal

Kirat Pal Singh

This paper describes the comparison between the hybrid adders. Adders are always used in many data-processing systems to perform fast arithmetic operations. The carry select adder (CSA) is a high speed adder. It provides good compromise between RCA and CLA. The ripple carry adder (RCA) has a most compact design but it takes longer computation time. The time critical applications uses carry look-ahead adder (CLA) to derive fast result but it required a large area. In this work we compared hybrid adders on the basis of delay, power and area. This design has been synthesized by Spartan 3 family with ...


A Low Cost Timing Generation Unit, Christopher Vochoska 2016 California Polytechnic State University – San Luis Obispo

A Low Cost Timing Generation Unit, Christopher Vochoska

Computer Engineering

No abstract provided.


Prosense, Johnny Favazza II, Casey Glasgow, Matt Epperson 2016 California Polytechnic State University, San Luis Obispo

Prosense, Johnny Favazza Ii, Casey Glasgow, Matt Epperson

Computer Engineering

This project aims to gather advanced data sets from MEMS sensors and GPS and deliver it to the user, who can capitalize on the data. The once negligible half-degree difference of your board barreling down a wave can be recorded from a gyro and exploited for the perfect turn. The exact speed dreaded by longboarders where speed wobbles turn into a road rash can be analysed and consequently avoided. Ascertaining the summit of your flight using combined GPS sensors from the ski ramp allows for the correct timing of tricks. When it comes to pursuing excellence in professional sports, amateur ...


Musictrakr, Benjamin Lin 2016 California Polytechnic State University, San Luis Obispo

Musictrakr, Benjamin Lin

Computer Engineering

MusicTrackr is an IoT device that musicians attach to their instruments. The device has a start and stop button that allows users to record their playing sessions. Each recorded session is sent wirelessly to a cloud database. An accompanying website displays all of the recorded sessions, organized by date. After picking a specific date, the user can view graphs showing total practice time and average session length as well play back any recordings during that date. In addition, the user may add comments to any specific date or recording. Lastly, the user may tag a specific date with a color ...


El Capitán: Cal Poly Rose Float Digital Drive System, Gregory Raffi Baghdikian 2016 California Polytechnic State University, San Luis Obispo

El Capitán: Cal Poly Rose Float Digital Drive System, Gregory Raffi Baghdikian

Computer Engineering

In today’s world of smartphones, self-driving cars, and internet-connected coffee makers, it seems as if computers are contained in everything around us. These “embedded systems” have become critical components of our lives, improving everything about the things they control, from cost, to speed, to simplicity. One area that embedded systems has hardly gained a foothold is in the world of floatbuilding. Most of the floats in the Tournament of Roses Parade, including the one built jointly by Cal Poly San Luis Obispo and Cal Poly Pomona, are technologically very simple, using mostly analog components and rudimentary discrete digital logic ...


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