Investigating On Through Glass Via Based Rf Passives For 3-D Integration, 2018 Ningbo University
Investigating On Through Glass Via Based Rf Passives For 3-D Integration, Libo Qian, Jifei Sang, Yinshui Xia, Jian Wang, Peiyi Zhao
Mathematics, Physics, and Computer Science Faculty Articles and Research
Due to low dielectric loss and low cost, glass is developed as a promising material for advanced interposers in 2.5-D and 3-D integration. In this paper, through glass vias (TGVs) are used to implement inductors for minimal footprint and large quality factor. Based on the proposed physical structure, the impact of various process and design parameters on the electrical characteristics of TGV inductors is investigated with 3-D electromagnetic simulator HFSS. It is observed that TGV inductors have identical inductance and larger quality factor in comparison with their through silicon via counterparts. Using TGV inductors and parallel plate capacitors, a ...
A Basic, Four Logic Cluster, Disjoint Switch Connected Fpga Architecture, 2018 California Polytechnic State University, San Luis Obispo
A Basic, Four Logic Cluster, Disjoint Switch Connected Fpga Architecture, Joseph Prachar
This paper seeks to describe the process of developing a new FPGA architecture from nothing, both in terms of knowledge about FPGAs and in initial design material. Specifically, this project set out to design an FPGA architecture which can implement a simple state machine type design with 10 inputs, 10 outputs and 10 states. The open source Verilog-to-Routing FPGA CAD flow tool was used in order to synthesize, place, and route HDL files onto the architecture. This project was completed in terms of the spirit of the original goals of implementing an FPGA from scratch. Although, the project resulted in ...
Bicycle Power Meter, 2018 California Polytechnic State University, San Luis Obispo
Bicycle Power Meter, Andrew Mcguan
No abstract provided.
Genetic Algorithm Amplifier Biasing System (Gaabs): Genetic Algorithm For Biasing On Differential Analog Amplifiers, 2018 California Polytechnic State University, San Luis Obispo
Genetic Algorithm Amplifier Biasing System (Gaabs): Genetic Algorithm For Biasing On Differential Analog Amplifiers, Sean Whalen
Genetic Algorithm Amplifier Biasing System (GAABS) - Senior Project Analysis
Summary of Functional Requirements
This project integrates LTSpice with a python script that runs a genetic algorithm to bias a differential amplifier. The system biases the amplifier with 2 different voltages, the base voltage for the PNP BJTs of the active loads and a voltage controlling the current of the current sink. The project runs via a python script, gets data from LTSpice’s command line call, and iteratively runs until the system is biased to achieve the greatest gain on an arbitrary input voltage.
Some of the main ...
Roborodentia Robot: Treadbot, 2018 California Polytechnic State University, San Luis Obispo
Roborodentia Robot: Treadbot, Stephen C. Schmidt
This document is a summary of my contest entry to the 2018 Cal Poly Roborodentia competition. It is meant to be a process overview and design outline of the mechanical, electrical, and software components of my robot.
Automating Knife-Edge Method Of Thz Beam Characterization, 2018 Portland State University
Automating Knife-Edge Method Of Thz Beam Characterization, Christopher Charles Faber
Undergraduate Research & Mentoring Program
The goal of this project is to create a time and cost-effective solution for THz beam profiling.
The knife edge method of beam characterization is a technique to verify the intensity profile of a beam involving traveling a blade orthogonal to the beam path and measuring transmission in successive steps. We use a vector network analyzer (VNA) to measure S21 transmission from a THz source. Manual implementation of this method was time-consuming and inefficient.
Project hardware includes an Arduino, a motor shield, and a ball screw linear rail with stepper motor actuator. Software was created in LabView and data is ...
"Improving System-On-Chip Test Networks For: Bandwidth, Security, And Power", 2018 Southern Methodist University
"Improving System-On-Chip Test Networks For: Bandwidth, Security, And Power", Saurabh Gupta
Computer Science and Engineering Theses and Dissertations
Modern System-on-Chips (SoCs) provide benefits such as reduction in overall system cost, and size, increased performance, and lower power consumption. Increasing complexity of these Integrated Circuits (ICs) has resulted in a higher probability of manufacturing defects. Manufacturing defects can result in the faulty operation of a system. Thus, it is essential to test an IC after it is manufactured to detect any possible faults in it. These SoCs include on-chip embedded instruments that can be used for test, debug, diagnosis, validation, monitoring, characterization, configuration, or functional purposes. IEEE 1687 Std. (IJTAG) provides a standard interface for the reconfigurable access and ...
Automatic Testing In The United States Air Force, 2018 University of Arkansas, Fayetteville
Automatic Testing In The United States Air Force, Pearson Wade
Computer Science and Computer Engineering Undergraduate Honors Theses
The need for standardized Automatic Testing Equipment in the United States Department of Defense has brought about new policies and procedures within entities like the United States Air Force. The diversity and lifespan of systems such as jets, missiles, drones, and other electronics have brought on the need for a new system known as the Versatile Depot Automatic Test Station, or VDATS. The VDATS handles the automatic testing of replaceable digital circuits from different systems. I was introduced to this system firsthand during my time as an intern at Tinker AFB, Oklahoma. This new standardized approach to testing a diverse ...
Comparison Of Data Transfer Alternatives In Asynchronous Circuits, 2018 University of Arkansas, Fayetteville
Comparison Of Data Transfer Alternatives In Asynchronous Circuits, Mark Howard
Computer Science and Computer Engineering Undergraduate Honors Theses
Digital integrated circuits (ICs) have become progressively complex in their functionality. This has sped up the demand for asynchronous architectures, which operate without any clocking scheme, considering new challenges in the timing of synchronous systems. Asynchronous ICs have less stringent environmental constraints and are capable of maintaining reliable operation in extreme environments, while also enjoying potential benefits such as low power consumption, high modularity, and improved performance. However, when the traditional bus architecture of synchronous systems is applied to asynchronous designs, handshaking protocols required for asynchronous circuit operation result in significantly increased power consumption, offsetting the low power benefit of ...
Asynchronous Circuit Stacking For Simplified Power Management, 2018 University of Arkansas, Fayetteville
Asynchronous Circuit Stacking For Simplified Power Management, Andrew Lloyd Suchanek
Theses and Dissertations
As digital integrated circuits (ICs) continue to increase in complexity, new challenges arise for designers. Complex ICs are often designed by incorporating multiple power domains therefore requiring multiple voltage converters to produce the corresponding supply voltages. These converters not only take substantial on-chip layout area and/or off-chip space, but also aggregate the power loss during the voltage conversions that must occur fast enough to maintain the necessary power supplies. This dissertation work presents an asynchronous Multi-Threshold NULL Convention Logic (MTNCL) “stacked” circuit architecture that alleviates this problem by reducing the number of voltage converters needed to supply the voltage ...
Security Analysis Of The Uconn Husky One Card, 2018 University of Connecticut
Security Analysis Of The Uconn Husky One Card, Trevor Phillips
Honors Scholar Theses
The “Husky One Card” is the name given to student IDs at the University of Connecticut. It can identify students, faculty, and staff in a variety of situations. The One Card is used for meal plans, Husky Bucks (an equivalent of money, but valid only in the Storrs area), residence hall/ university facility access, and student health services. The current Husky One Card consists of a picture identification on the front and a standard 1-dimensional barcode and 3-track magnetic strip on the back.
The goal of this thesis is to investigate the feasibility of cloning Husky One Cards, the ease ...
Skybridge-3d-Cmos: A Fine-Grained Vertical 3d-Cmos Technology Paving New Direction For 3d Ic, 2018 Electircal and Computer Engineering
Skybridge-3d-Cmos: A Fine-Grained Vertical 3d-Cmos Technology Paving New Direction For 3d Ic, Jiajun Shi
2D CMOS integrated circuit (IC) technology scaling faces severe challenges that result from device scaling limitations, interconnect bottleneck that dominates power and performance, etc. 3D ICs with die-die and layer-layer stacking using Through Silicon Vias (TSVs) and Monolithic Inter-layer Vias (MIVs) have been explored in recent years to generate circuits with considerable interconnect saving for continuing technology scaling. However, these 3D IC technologies still rely on conventional 2D CMOS’s device, circuit and interconnect mindset showing only incremental benefits while adding new challenges reliability issues, robustness of power delivery network design and short-channel effects as technology node scaling.
Skybridge-3D-CMOS (S3DC ...
Implementation Of Switching Circuit Models As Vector Space Transformations, 2017 Southern Methodist University
Implementation Of Switching Circuit Models As Vector Space Transformations, David Kebo Houngninou
Computer Science and Engineering Theses and Dissertations
Modeling of switching circuits is the foundation for many Electronic Design Automation (EDA) tasks and is commonly used at various phases of the design flow for tasks such as simulation, justification, and other analyses. State-of-the-art simulation tools are based on discrete event algorithms using switching algebraic models and are highly optimized and mature. Symbolic simulation may also be implemented using a discrete event approach, or other approaches based on extracted functional models. The common foundation of modern simulation tools is that of a switching or Boolean algebraic model that may be augmented with timing information. Justification using switching circuit models ...
Real Time And High Fidelity Quadcopter Tracking System, 2017 California Polytechnic State University, San Luis Obispo
Real Time And High Fidelity Quadcopter Tracking System, Tyler Mckay Hall
This project was conceived as a desired to have an affordable, flexible and physically compact tracking system for high accuracy spatial and orientation tracking. Specifically, this implementation is focused on providing a low cost motion capture system for future research. It is a tool to enable the further creation of systems that would require the use of accurate placement of landing pads, payload acquires and delivery. This system will provide the quadcopter platform a coordinate system that can be used in addition to GPS.
Field research with quadcopter manufacturers, photographers, agriculture and research organizations were contact and interviewed for information ...
Design And Simulation Of An 8-Bit Successive Approximation Register Charge-Redistribution Analog-To-Digital Converter, 2017 University of Texas at Tyler
Design And Simulation Of An 8-Bit Successive Approximation Register Charge-Redistribution Analog-To-Digital Converter, Sumit K. Verma
Electrical Engineering Theses
The thesis initially investigates the history of the monolithic ADCs. The next chapter explores the different types of ADCs available in the market today. Next, the operation of a 4-bit SAR ADC has been studied. Based on this analysis, an 8-bit charge-redistribution SAR ADC has been designed and simulated with Multisim (National Instruments, Austin, TX). The design is divided into different blocks which are individually implemented and tested. Level-1 SPICE MOSFET models representative of 5μm devices were used wherever individual MOSFETs were used in the design. Finally, the power dissipation during the conversion period was also estimated. The supply voltage ...
Measurement Of Speed Of Sound Profile Using Laaces Balloon, 2017 McNeese State University
Measurement Of Speed Of Sound Profile Using Laaces Balloon, Zhuang Li, Brett Schaefer, Brian Schaefer, William Dever, Tyler Morgan, Matthew Foltz
2017 Academic High Altitude Conference
The goal of this mission is to test the speed of sound at different altitudes and ultimately at a maximum height of 100,000 feet (30 km). In conjunction with this testing, environmental parameters including temperature, pressure, and humidity are measured and used to calculate the speed of sound to compare to the measured results. The team constructed the payload “Dorothy” using polystyrene foam due to its lightweight and thermal isolation property. An ultrasonic sensor with a reflection mirror were installed outside payload box to measure speed of sound. All the sensors were calibrated. Software for the project was developed ...
Lmproving Microcontroller And Computer Architecture Education Through Software Simulation, 2017 The University of Western Ontario
Lmproving Microcontroller And Computer Architecture Education Through Software Simulation, Kevin Brightwell
Electronic Thesis and Dissertation Repository
In this thesis, we aim to improve the outcomes of students learning Computer Architecture and Embedded Systems topics within Software and Computer Engineering programs. We develop a simulation of processors that attempts to improve the visibility of hardware within the simulation environment and replace existing solutions in use within the classroom. We designate a series of requirements of a successful simulation suite based on current state-of-the-art simulations within literature. Provided these requirements, we build a quantitative rating of the same set of simulations. Additionally, we rate our previously implemented tool, hc12sim, with current solutions. Using the gaps in implementations from ...
Energy And Performance Balancing Architecture For Asynchronous Data Processing Platforms, 2017 University of Arkansas, Fayetteville
Energy And Performance Balancing Architecture For Asynchronous Data Processing Platforms, Chien-Wei Lo
Theses and Dissertations
The semiconductor industry has been increasingly focused on the energy consumption and heat generation in CMOS-based integrated circuits (ICs) for its dominating impact on the system performance and reliability. Without clock-related timing constraints, asynchronous circuits have demonstrated unique flexibility in performance-energy tradeoffs compared to synchronous designs. This dissertation work presents the architecture capable of balancing energy and performance for asynchronous digital signal processing circuits using the Multi-Threshold NULL Convention Logic (MTNCL). Architecture implementing user-configurable adaptive dynamic voltage scaling (DVS) and data processing core disabling based on the detection and parameterization of system throughput are developed for MTNCL parallel homogeneous and ...
One-To-Cloud One-Time Pad Data Encryption: Introducing Virtual Prototyping With Pspice, 2017 Dublin Institute of Technology
One-To-Cloud One-Time Pad Data Encryption: Introducing Virtual Prototyping With Pspice, Paul Tobin, Lee Tobin, Roberto Gandia Blanquer Dr, Michael Mckeever, Jonathan Blackledge Professor
In this paper, we examine the design and application of a one-time pad encryption system for protecting data stored in the Cloud. Personalising security using a one-time pad generator at the client-end protects data from break-ins, side-channel attacks and backdoors in public encryption algorithms. The one-time pad binary sequences were obtained from modified analogue chaos oscillators initiated by noise and encoded client data locally. Specific ``one-to-Cloud'' storage applications returned control back to the end user but without the key distribution problem normally associated with one-time pad encryption. Development of the prototype was aided by ``Virtual Prototyping'' in the latest version ...
Poly Drop, 2017 California Polytechnic State University, San Luis Obispo
Poly Drop, Zachary T. Scott, Lilly J. Paul
Poly Drop is a software interface to control an Open Drop digital micro-fluidics system. We obtained a hardware system from Gaudi labs. Our task was to create a Graphical User Interface that made the control of the device easier and more automated for better testing. We created software that had 3 parts: a control GUI, arduino code to control the hardware, and Image Analysis that gives the user information such as location and color of liquid drops as they move across the electrode grid of the Open Drop system. The GUI was developed using Java Swing. The communication between the ...